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Input Test Waveforms and Measurement Levels
AC
DRIVING
LEVELS
2.4V
0.45V
2.0
0.8
AC
MEASUREMENT
LEVEL
t R , t F < 3 ns (10% to 90%)
Output Test Load
DEVICE
UNDER
TEST
30 pF
AC Waveforms
Two different timing diagrams are shown below. Waveform 1 shows the SCK signal being low
when CS makes a high-to-low transition, and Waveform 2 shows the SCK signal being high
when CS makes a high-to-low transition. Both waveforms show valid timing diagrams. The setup
and hold times for the SI signal are referenced to the low-to-high transition on the SCK signal.
Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2 shows tim-
ing that is compatible with SPI Mode 3.
Waveform 1 – Inactive Clock Polarity Low and SPI Mode 0
t CS
CS
t CSS
t WH
t WL
t CSH
SCK
t V
t HO
t DIS
SO
HIGH IMPEDANCE
VALID OUT
HIGH IMPEDANCE
SI
t SU
VALID IN
t H
Waveform 2 – Inactive Clock Polarity High and SPI Mode 3
t CS
CS
t CSS
t WL
t WH
t CSH
SCK
t V
t HO
t DIS
SO
HIGH Z
VALID OUT
HIGH IMPEDANCE
SI
t SU
VALID IN
t H
14
AT45DB081B
2225J–DFLSH–2/08
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